What are PECL and LVPECL?
什么是差分晶振的PECL和LVPECL？
• PECL stands for “Positive Emitter Coupled Logic”.PECL are differential logic outputs commonly used in high-speed clock distribution circuits. PECL requires a +5 V supply .
•PECL代表“正發(fā)射極耦合邏輯”.PECL是常用于高速時(shí)鐘分配電路的差分邏輯輸出。 PECL需要+5 V電源。
• Low Voltage PECL (LVPECL) denotes PECL circuits designed for use with 3.3V or 2.5V supply,the same supply voltage as for low voltage CMOS devices.
•低壓PECL（LVPECL）表示設(shè)計(jì)用于3.3V或2.5V電源的PECL電路，電源電壓與低壓CMOS器件相同。
• Taitien offers LVPECL output crystal oscillators in both 3.3V and 2.5V supplies
泰藝晶振提供3.3V和2.5V電源的LVPECL輸出晶體振蕩器

Pros/Cons of PECL Output
PECL輸出的優(yōu)點(diǎn)/缺點(diǎn)
• Advantages :
• 好處：
– Very good jitter performance due to large voltage swing
- 由于大電壓擺動(dòng)，具有非常好的抖動(dòng)性能
– Ideal use in high-speed circuits
- 理想用于高速電路
– Capable of driving long transmission lines
- 能夠驅(qū)動(dòng)長(zhǎng)傳輸線(xiàn)

• Drawbacks:
• 缺點(diǎn)：
– Larger power consumption due to differential output and external DC biasing compared to single-ended output
- 與單端輸出相比，差分輸出和外部直流偏置會(huì)產(chǎn)生更大的功耗
– Incompatible with 1.8V supply
- 與1.8V電源不兼容

Recommended PECL Termination Circuit
推薦的PECL終端電路

Each output is terminated with a 50 ? resistor to a termination voltage of (Vdd – 2V).
每個(gè)輸出端接50Ω電阻，端接電壓為（Vdd - 2V）。

What is LVDS Output?
什么是LVDS輸出？
• LVDS stands for Low Voltage Differential Signaling,centered around operating voltage of 1.2V,regardless of power supply.
•LVDS代表低壓差分信號(hào)，以1.2V的工作電壓為中心，與電源無(wú)關(guān)。
• LVDS technology is defined by the ANSI/TIA/EIA-644 industry standard.
•LVDS技術(shù)由ANSI / TIA / EIA-644行業(yè)標(biāo)準(zhǔn)定義。
• Taitien has many crystal oscillator product lines with LVDS output options at 3.3V and 2.5V supplies.
•Taitien擁有許多晶體振蕩器產(chǎn)品系列，具有3.3V和2.5V電源的LVDS輸出選項(xiàng)。

Pros/Cons of LVDS Output
LVDS輸出的優(yōu)點(diǎn)/缺點(diǎn)
• Advantages:
• 好處：
– Lower power consumption compared to PECL outputs due to smaller voltage swings (typically ~350mV)
- 由于較小的電壓擺幅（通常約為350mV），與PECL輸出相比功耗更低
– Less susceptible to noise
- 不易受噪音影響
– Lower EMI emissions compared to CMOS/TTL
- 與CMOS / TTL相比，EMI輻射更低
• Drawbacks:
• 缺點(diǎn)：
– Reduced jitter performance compared to PECL
- 與PECL相比，抖動(dòng)性能降低

Where is LVDS used?
LVDS在哪里使用？
The LVDS standard was created to address applications in the data communications, telecommunications,server, peripheral and computer markets where high-speed data transfer is necessary.
LVDS標(biāo)準(zhǔn)旨在滿(mǎn)足數(shù)據(jù)通信，電信，服務(wù)器，外圍設(shè)備和計(jì)算機(jī)市場(chǎng)中需要高速數(shù)據(jù)傳輸?shù)膽?yīng)用。

Recommended LVDS Termination Circuit
推薦的LVDS終端電路

A single 100 ? termination resistor is needed. Some receiver ICs may include the resistor internally.
需要一個(gè)100Ω端接電阻。一些接收器IC可能在內(nèi)部包含電阻器。

Signal Level Comparison
信號(hào)電平比較